The Cambrian Explosion of AI Chip Architectures
Since John Hennessy and David Patterson's 2018 Turing Lecture predicted a Cambrian explosion of domain-specific architectures, the landscape has delivered: GPUs, TPUs, LPUs, NPUs, DPUs, ASICs, wafer-scale engines, and more. This survey examines the philosophies, architectures, scaling methods, and software stacks of the key contenders—NVIDIA, AMD, Google, Amazon, Cerebras, and Groq—focusing on how each tackles the memory wall and the shift from matrix-matrix to matrix-vector operations in AI inference.
The architecture problem here is moving the numbers to where the matmuls happens fast enough.
- hliyan
Is anyone working on running neural networks on CPU architectures that are not limited by synchronous clock signals? Organic neural networks are inherently asynchronous and signals propagate through different parts of the network at their own pace.
- ilaksh
Those are amazing accomplishments but I am more interested in research developments in things like In-Memory (Analog) or other different approaches.
Companies like EnCharge, Mythic, etc.
And much more efficient devices like RRAM, MRAM, and FETs. Like FE-FETs with AlScN.
The stuff just coming out of research or still in research is more exciting in terms of the potential for truly huge efficiency and performance boosts.
Taalas is interesting also because of it's efficiency and speed. Guess it was just purchased by AMD.
- hadlock
Maybe it's just me, but between the extremely thin font and layout design, I find this extremely difficult to parse. Overuse and improper use of italics is confusing as well.
- pure_magic
This text is most likely AI-generated. Borderline unreadable.
- paaloeye
Not too shabby, but it shouldn't have been like 3 posts