Samsung's zHBM Stacks Memory Directly on AI Chips for 8x Performance
Samsung Debuts zHBM Prototype, Stacking Memory Directly on AI Accelerators
Samsung unveiled zHBM at FMS 2026, a 3D architecture that vertically stacks HBM on top of AI accelerators to cut data travel distance. The company claims up to eight times the performance of HBM5, three times better performance per watt, and over 50% lower thermal resistance. Samsung also showed zNAND-O, 400-plus-layer V10 BV-NAND, HBM4E, HBM5, and LPDDR5X-PIM, positioning itself as the only IDM offering a one-stop AI memory solution.
We can provide integrated services from the product design stage through mass production, helping customers shorten development cycles while optimizing performance and power efficiency.
- vkaku
A lot of the AI progress is stalled because these chips do not handle thermal contraction/expansion well at all, and end up permanently destroying these chips. HBM has been a failure at this scale with chips getting destroyed every 4 months or so during operations.
I'd like to see some actual science saying, here was the problem, here's how we solved it, here's the AFR data, here's this running after X cycles etc. Nobody has done this reliably yet. That entire industry is hiding the bodies.
- marsx-dev
How much of the benefit here comes from shorter data paths, versus simply being able to fit more memory closer to the accelerator?
- tancop
Where is the HBM controller in this design? Stacked in a middle layer or integrated into the main GPU die?